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Si4430/31/32-B1
Rev 1.1
19
Figure 4. SPI TimingREAD Mode
The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An example burst write
transaction is illustrated in Figure 5 and a burst read in Figure 6. As long as nSEL is held low, input data will be
latched into the Si4430/31/32 every eight SCLK cycles.
Figure 5. SPI TimingBurst Write Mode
Figure 6. SPI TimingBurst Read Mode
nSEL 
SCLK 
SDI 
First Bit
Last Bit
A0
D7
=X 
DO 
D7
A1
A2
First Bit
Last Bit 
A3
D6
=X 
D5
=X 
D4
=X 
D3
=X 
D2
=X 
D1
=X 
D0
=X 
D6  D5  D4  D3   D2  D1  D0 
A4 
A5 
A6 
RW
=0 
nSEL 
SCLK 
SDI 
First Bit
A0 
D7
=X 
A1 
A2 
A3 
D6
=X 
D5
=X 
D4
=X 
D3
=X 
D2
=X 
D1
=X 
D0
=X 
A4 
A5 
A6 
RW
=1 
Last Bit
D7
=X 
D6
=X 
D5
=X 
D4
=X 
D3
=X 
D2
=X 
D1
=X 
D0
=X 
SEL 
CLK 
DI 
First Bit
Bi
A0 
D7
=X 
DO 
D7
A1 
A2 
First Bit
A3 
D6
=X 
D
=X 
D4
=X 
D3
=X 
D2
=X 
D1
=X 
D0
=X 
D6  D5  D4  D3   D2  D1  D0
A4 
A5 
A6 
RW
=0 
D7  D6  D5  D4   D3   D2   D1  D0
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